1. Field of the Invention
The present invention relates to a sensing circuit for a memory device, and more particularly to a current sensing type sensing circuit for reading data stored in an electrical erasable programmable memory (EEPROM).
2. Description of the Prior Art
It is known that an electrical erasable programmable memory (abbreviated EEPROM) includes a number of memory cells therein and is capable of storing data in the memory cells. The data stored in the EEPROM is either in the form of conductive or non-conductive state, and the data state may be sensed by a sensing circuit.
FIG. 1 is a schematic circuit diagram showing a conventional memory cell of an EEPROM. The memory cell 1 of the EEPROM is mainly composed of a MOS transistor 11 and an EEMOS transistor 12. The EEMOS transistor 12 serves as a storage element for the memory cell. The logic level at point VD is low voltage level when the memory cell circuit is in conductive status, which means that the data stored in the memory cell is logic low level "0". On the contrary, the point VD is at floating level when the memory cell circuit is in non-conductive status, which means that the data stored in the memory is logic high level "1".
A threshold voltage Vt of the EEMOS transistor determines whether the EEMOS transistor 12 is conductive or non-conductive. In case the threshold voltage Vt is larger than the gate voltage VG of the transistor, the EEMOS transistor will be non-conductive. On the contrary, in case the threshold voltage Vt is lower than the gate voltage VG of the transistor, the EEMOS transistor will be conductive. So, the data stored in the memory cell may be detected by a sensing circuit by detecting the voltage level at point VD.
During reading the data stored in the memory cell of the EEPROM, the relative points of the EEPROM memory cell are listed below:
______________________________________ read mode VG VS VD VCG ______________________________________ 1 0 V 0 V 2 V 5 V 0 0 V 0 V 0 V 5 V ______________________________________
As mentioned above, the data stored in the memory cell may be read by a sensing circuit by sensing the voltage level of the memory cell of the EEPROM. Once the sensing circuit detects the data, the data will be sent to an amplifying circuit which is used to amplify the accessed data. Typically, the amplifying circuit is an inverted amplifying circuit.
FIG. 2 is a schematic circuit diagram of a prior art sense amplifying circuit, which mainly includes a PMOS transistor 21, a NMOS transistor 22, two inverters 23 and 24. The PMOS transistor 21 serves as a pull-up transistor. The gate of the NMOS 22 is controlled by a bias control signal CO. The source of the NMOS 22 is coupled to the memory cell of the EEPROM for receiving the data sent from the EEPROM.
In operation, the voltage level at intersection point between the PMOS 21 and the NMOS 22 may be charged or discharged by means of the operation of the PMOS 21 and the NMOS 22. The voltage level may be detected by the inverters 23 and 24. However, it is found that the sensing speed of this prior art sensing circuit is slow because that the voltage charging operation is limited. Especially, the discharging speed of the memory cell is rather slow during detecting logic level "0" because that the discharging speed of the circuit is low.